Projects
Project #1
Project description
(including due dates) is here.
The C++ preliminary framework with
basic classes and the circuit netlist parser are here.
Handout on Timing Wheel.
For the first part of this project you will need the following three
circuits. Use a unit-delay model for all the logic gates that are used
in any of these circuits.
-- circuit_1.map
-- circuit_2.map
-- circuit_3.map
For the second part, you will work with the following circuits and
fault-input files.
-- circuit_4.map
-- circuit_5.map
-- circuit_6.map
-- faults_4.txt
-- faults_5.txt
-- faults_6.txt
Project #2
Project description
(including due date) is here.
The VHDL tutorial on how
to use Altera's CAD tool is here.
Project #3
In this project you will be
assigned a testing topic/problem. You will have to search (IEEEXplore,
ACM Digital Library, Internet) for the most recent journal and
conference papers (published within the last 4 years) on your assigned
topic. You
will then make a presentation (15 slides, 20 minutes) on the most
relevant solution and present it in front of the class.
Project ideas for extra credit
Description of
projects for extra credit is here.