Course Introduction

Catalog Description
This course is an overview of computer hardware systems, with emphasis on modern processor design. Topics include performance analysis, RISC-V assembly language, arithmetic logic units, datapath and control of processor architectures, pipelining, and memory and I/O devices.

Instructor
Cristinel (Cris) Ababei
cristinel.ababei@marquette.edu
Phone: 414-288-5720
Office: Haggerty Hall, #220

Syllabus
For course goals and objectives, policies, and a tentative outline please see the syllabus on D2L.

Textbook

[1] David A. Patterson and John L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, The Morgan Kaufmann Series in Computer Architecture and Design, 2nd Ed., 2020. (Required). Companion website.

Lectures

Lecture 1: Computer abstractions and technology (Ch.1)
--> Slides
--> Moore's Law
Lecture 2: Instructions: Language of the Computer (Ch.2)
--> Slides
--> RISC-V-Reference-Data-Green-Card
Lecture 3: The Processor - Single Cycle: Datapath and Control (Ch.4)
--> Slides
Lecture 4: The Processor - Pipelining: Hazards (Ch.4)
--> Slides
Lecture 5: Introduction to VHDL (needed for Project #2)
--> Slides
--> Light introduction to FPGAs (Lecture notes)
--> FPGA Details (Slides)
Lecture 6: Arithmetic for Computers - Building the ALU (Ch.3 + Appendix A)
--> Slides a)
--> Slides b)
Lecture 7: Memory Hierarchy (Ch.5)
--> Slides
Lecture 8: From ILP to Parallel Processors (Ch.6)
--> Slides
--> Slides (part 2 on Networks-on-Chip)

Projects

Project #1 - Implement a sorting algorithm using RISC-V assembly. Validate it using the RARS simulator.
--> Step 1
Download the latest .jar RARS simulator:
https://github.com/TheThirdOne/rars/releases
--> Step 2
Learn the basics through examples. Use the following examples; read code and the comments therein, simulate, and observe operation:
1) hello, 2) print name, 3) add constant to number, 4) find_max, 5) generate Fibonacci numbers
--> Step 3
Read about environment calls that can be used to print to console and to exit the program:
Environment Calls
--> Step 4
Write your own assembly implementation of the assigned algorithm (see D2L for details).

Project #2 - Describe in VHDL the RISC-V single cycle processor.
--> Step 1
Download and install Xilinx Vivado, the free version. Note that you may have it already installed, from digital logic course. You will need to create a free user account with Xilinx in order to be able to download the installer. During the installation, make sure you select from Devices, only 7 Series, Artix 7 device family, and un-select all others to minimize occupied disk space.
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2021-2.html
--> Step 2 (optional)
Brush up your VHDL programming skills, whcih you learned in the digital logic course. It is up to you how to do this. However, here are a couple of possibly helpful pointers:
--Jan Van der Spiegel's VHDL primer (a very nice first time exposure to VHDL concepts):
VHDL Primer at Penn State
--Additional design examples to create new Vivado projects that you should simulate to get even more familiar with simulation of VHDL testbenches in Vivado.
Design examples source files ("fourbit adder", "fourbit counter", and "edge detection circuit")
--Read and do labs 1-11 available at this website (i.e., the labs from the VHDL 2015x column):
http://www.xilinx.com/support/university/vivado/vivado-teaching-material/hdl-design.html
--Watch the video tutorials from the link below. Some of these tutorials are long. You do not need to know all the details. For now, just get reasonably comfortable with the simulation features and basic synthesis features of Vivado.
http://www.xilinx.com/training/vivado/
--Read the following textbook for further details and insights into VHDL language - syntax and format. You will find examples including: registers, DFFs, multiplexers, counters, and testbenches.
VHDL tutorial by Peter Ashenden
--Read and complete (start to end) the Vivado Tutorial for Basys3 - do the simulation parts, skip the verification on the Bays 3 board:
http://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2015x/VHDL/docs-pdf/Vivado_Tutorial.pdf
Make sure you download also the files Tutorial.zip, which you need for this tutorial; note that the tutorial introduces the concept of testbenches as well:
http://www.xilinx.com/support/university/vivado/vivado-teaching-material/hdl-design.html (see VHDL 2015x column)
--> Step 3
Work on actual Project #2, part A, part B, and part C! (see D2L for details).

Resources

Conferences
-- International Symposium on High-Performance Computer Architecture (HPCA)
-- International Symposium on Computer Architecture (ISCA)
-- International Symposium on Microarchitecture (MICRO)
-- European Network on High Performance and Embedded Architecture and Compilation (HiPEAC)