|Chip Multiprocessors (CMPs)|
|REST Reliability Estimation for CMPs
This is a "push-button" tool for the estimation of lifetime reliability of network-on-chip based chip multiprocessors. The tool integrates gem5 full-system simulator, McPAT power calculator, HotSpot thermal simulator, Monte Carlo algorithm for MTTF computation, and required scripts (gem5 to mcpat, mcpat to hotspot). Currently it supports TDDB and NBTI aging failure mechanisms. This project also includes dynamic reliability management (DRM) using a combination of DVFS and thread migration techniques.
This tool implements an efficient bipartite-matching based heuristic for application remapping to facilitate fault-tolerance against processing element (PE) failures. It also includes a simulated annealing based implementation for comparison purposes.
|ReliableNOC Energy- and
reliability-aware mapping for regular NoC
Branch-and-bound (BB) algorithm to solve the problem of energy- and reliability-aware mapping for regular NoCs. Reliability is estimated by an efficient Monte Carlo algorithm based on the destruction spectrum of the network. The tool is developed on top of "nocmap 1.2" from CMU.
||VNOC 2.0 Versatile
This is a flexible trace-driven cycle-accurate simulator for homogeneous NoCs. It has integrated Orion 2 power model as well as a simple GUI, useful for debugging and displaying routers congestion. In addition, it has frequency throttle and frequency boost based DVFS (dynamic voltage and frequency scaling) implemented at router level. It is meant to be used as either an NoC simulation tool or a platform for implementing and investigating DVFS ideas.
based framework for 3D NoC architectures
This is a software framework to support the exploration of 3D NoC architectures with two and three layers: first and third layers host irregular floorplans and the middle layer is dedicated to implementing the communication infrastructure as a regular NoC.
(or irregular) NoC topology synthesis
Custom NoC topology synthesis tool. Main steps: simulated annealing based floorplanning (B*-tree representation), bipartite-matching based routers assignment, multicommodity flow based routing paths calculation (congestion minimization), and VNOC simulation (latency estimation).
|VnocDec Co-simulation of NoC and H.264 video
VnocDec = VNoC + H.264Dec is a full system simulation framework for a network-on-chip (NoC) based H.264 video decoder. This allows for the NoC to be exercised with real rather than synthetic traffic. Implementation done by my PhD student, M.G. Moghaddam.
|pro-NERDS (version 1.0): Network reconfiguration
of distribution systems
Efficient network reconfiguration of distribution systems for loss minimization. It is based on a minimum-cost maximum-flow algorithm. The tool also includes the famous Baran's reconfiguration algorithm (for comparison purposes) as well as DistFlow loss estimation technique.
|pro-PART (version 1.0): Extreme event screening for
This tool implements an efficient extreme event screening for power systems. It is based on cutsize and power-imbalance oriented partitioning.
||pro-DIRES (version 1.0): Minimum set of directional
This program implements a deterministic algorithm for the determination of the minimum break point set (MBPS) of directional relay networks based on k-trees of the network graphs.
|VLSI and FPGA circuits|
Net reordering and
multicommodity flow based global routing for FPGAs
This is an enhanced routing algorithm implemented on top of the VPR 4.3 tool. It changes the order in which nets are ripped-up and rerouted. Cost calculation is altered during wave expansions for two-pin nets based on the global routing solution obtained by solving an equivalent multicommodity flow problem.
|parallelVPR Parallel placement for
This is the multithreaded version of the simulated annealing based placement for FPGAs of VPR. The archive also includes all 20 testcases of VPR 4.3, and the largest testcases of VPR 5.0.
|TPR Three-dimensional Place and Route for FPGAs
This is a complete placement and routing tool for 3D FPGA architectures. The placer is partitioning based while the router is the 3D adaptation of the VPR 2D router.
This is an adapted version of the Edmonds-Karp relabelling mcmf algorithm , originally implemented by Igor Naverniouk. This adapted version allocates memory dynamically in order to use memory as needed.
 J. Edmonds, R.M. Karp, "Theoretical Improvements in Algorithmic Efficieincy for Network Flow Problems," J. ACM, vol. 19, pp. 248-264, 1972.
This is a "ported to C++" version of the famous scaling push-relabel CS2 mcmf algorithm of A.V. Goldberg . This C++ implementation is developed from the original C code.
 A.V. Goldberg, "An Efficient Implementation of a Scaling Minimum-Cost Flow Algorithm," J. Algorithms, vol. 22, pp. 1-29, 1997.
This is an efficient C++ implementation of a polynomial time approximation algorithm . It provides a clean and simple interface (for easy integration in bigger projects) for specifying the network (or graph) and the supplies and demands.
 G. Karakostas, "Faster approximation schemes for fractional multicommodity flow problems," ACM/SIAM SODA, pp. 166-173, 2002.