Active projects:

-- Uncertainty modeling and design methods for heterogeneous embedded systems.

This project introduces novel uncertainty modeling approaches and uncertainty-aware design methods for heterogeneous multicore embedded systems to address the increased design uncertainties due to process, voltage, temperature variations. We develop a multi-objective computer-aided design (CAD) automation framework, which incorporates several algorithmic innovations based on Monte Carlo techniques and evolutionary algorithms. (Funded by NSF. Project webpage here.)

-- Lifetime reliability aware design of network-on-chip based multiprocesor systems-on-chip.
Future integrated chip multiprocessors (CMPs) with hundreds of IP cores will contain billions of transistors and wires. Many transistors will be dead after manufacturing and the rest will be subject to the effects of wearout mechanisms (e.g., electromigration, EM, thermal cycling TC, negative bias temperature instability, NBTI, time-dependent dielectric breakdown, TDDB), which will result in performance degradation and eventual device/system failure. To address these issues, our goal is to develop algorithmic and circuit/architecture-level solutions to facilitate fault-tolerance and adaptiveness. (Funded by NSF. Project webpage here.)

-- Analysis and optimization of power systems.
In fulfilling the vision of a smart self-healing electric grid (that can automatically respond to disturbances while continuously optimizing the overall performance), features such as flexible reconfiguration, superfast simulators, advanced visualization tools, and adaptive response systems are indispensable. Our current focus is on developing an energy and power simulation framework for buildings and districts. (Funded by M-WERC)

-- Drones, from the ground up.  

Less active projects:

-- Network-on-chip synthesis
To address the "global interconnect delay problem" and to enable increased communication concurrency, network-on-chip (NoC) emerged as a promising new design paradigm for increasingly complex systems-on-chip (SoCs). Our goal is to develop and implement a versatile software framework for efficient custom NoC topology synthesis. We also are interested in exploring new NoC architectural ideas (such as 3D integration) and power management schemes (employing dynamic voltage and frequency scaling, DVFS).

-- Electronic design automation for VLSI and FPGA circuits
Due to the continuous increase of circuits complexity, one of the current challenges faced by the EDA community is the long computational runtimes of placement and routing algorithms. Our current focus is on speeding-up such algorithms by parallelization based on multithreading employing multi-core processors and graphics processor units (GPU).

-- Reconfigurable and parallel computing
Our current goal is to employ partial dynamic reconfiguration techniques to develop a network-on-chip based reconfigurable computing platform.