single_cycle_cpu Project Status (12/03/2012 - 21:51:33)
Project File: lab11_SCC.xise Parser Errors: No Errors
Module Name: single_cycle_cpu Implementation State: Programming File Generated
Target Device: xc6slx45-3csg324
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
429 Warnings (0 new, 0 filtered)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 46 54,576 1%  
    Number used as Flip Flops 46      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 93 27,288 1%  
    Number used as logic 87 27,288 1%  
        Number using O6 output only 47      
        Number using O5 output only 33      
        Number using O5 and O6 7      
        Number used as ROM 0      
    Number used as Memory 0 6,408 0%  
    Number used exclusively as route-thrus 6      
        Number with same-slice register load 0      
        Number with same-slice carry load 6      
        Number with other load 0      
Number of occupied Slices 29 6,822 1%  
Nummber of MUXCYs used 56 13,644 1%  
Number of LUT Flip Flop pairs used 94      
    Number with an unused Flip Flop 48 94 51%  
    Number with an unused LUT 1 94 1%  
    Number of fully used LUT-FF pairs 45 94 47%  
    Number of unique control sets 5      
    Number of slice register sites lost
        to control set restrictions
26 54,576 1%  
Number of bonded IOBs 10 218 4%  
    Number of LOCed IOBs 10 10 100%  
Number of RAMB16BWERs 0 116 0%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.26      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Dec 3 21:49:45 20120429 Warnings (0 new, 0 filtered)4 Infos (0 new, 0 filtered)
Translation ReportCurrentMon Dec 3 21:49:51 2012000
Map ReportCurrentMon Dec 3 21:50:20 2012006 Infos (6 new, 0 filtered)
Place and Route ReportCurrentMon Dec 3 21:50:37 2012003 Infos (3 new, 0 filtered)
Power Report     
Post-PAR Static Timing ReportCurrentMon Dec 3 21:50:48 2012004 Infos (4 new, 0 filtered)
Bitgen ReportCurrentMon Dec 3 21:51:28 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Dec 3 21:51:28 2012
WebTalk Log FileCurrentMon Dec 3 21:51:33 2012

Date Generated: 12/03/2012 - 21:51:33