Lecture Slides, Readings |
VHDL Code, Some Readings |
Videos |
Lecture 1: FPGAs (field
programmable gate arrays) -- Light introduction to FPGAs: lec01_fpga_intro_part1.pdf -- FPGA Details, Slides: lec01_fpga_details_part2.pdf -- Readings: [1] DE2-115 User Manual [2] DE1-SoC User Manual [3] Basics of Reconfigurable Computing |
How to install
Quartus Prime How to program the DE1-SoC board How to copy HPS executable to microSD card |
|
Lecture 2: Introduction to Quartus II
Software via Examples -- Example #1: Simple four bit adder circuit (structural vs. behavioral) - lec02_fourbit_adder.pdf -- Example #2: Edge detection circuit of rising edge (Mealy vs. Moore FSMs) - lec02_edge_detector_mealy_moore.pdf, block diagram -- Example #3: Fourbit counter (structural vs. behavioral) - lec02_fourbit_counter.pdf -- Readings: [1] Pong P. Chu, FPGA Prototyping by VHDL Examples, Wiley, 2008. (Chapters 1,2,3) [2] VHDL Primer at Penn State (very nice first exposure to VHDL concepts) [3] Supplemental material for lecture 2: lec02_supplemental_VHDL.pdf [4] Links related to VHDL tutorials on dejazzer's EE-478 website |
fourbit_adder_vhdl.zip fourbit_adder_vhdl_behavioral.zip edge_detection_vhdl.zip fourbit_counter_vhdl.zip fourbit_counter_vhdl_behavioral.zip |
Hexadecimal to seven-segment (video 1) Edge detection circuit (video 2) |
Lecture 3: Concepts of VHDL (from
A to Z) -- VHDL Basics (entity, behavioural, structural): lec03_a_VHDL_intro.pdf -- Concurrent and sequential statements (component, concurrency, process): lec03_b_conc_seq.pdf -- Combinational and sequential circuits I (muxes, coders, decoders, registers, counters, FSMs): lec03_c_sequential_1.pdf -- Sequential circuits II (FSMs, if-then-else, case, for-loop, wait, etc.): lec03_d_sequential_2.pdf -- Functions, Procedures, Packages: lec03_e_packages_1.pdf, lec03 e_packages_2.pdf, lec03_e_packages_3.pdf -- VHDL coding for synthesis: lec03 f_coding_for_synthesis.pdf |
StopWatch (video 3) |
|
Lecture 4: More on FSMs: ASM,
FSMD, ASMD -- Finite State Machine with Datapath (FSMD): lec04_fsmd.pdf -- Example #4: Fibonacci number circuit - See lec04_fsmd.pdf -- Example #5: Period counter - See lec04_fsmd.pdf -- Example #6: Division circuit - See lec04_fsmd.pdf -- Example #7: Binary to BCD converter - See lec04_fsmd.pdf -- Example #8: Accurate low-frequency counter - See lec04_fsmd.pdf -- Example #9: Fourbit multiplier - See lec04_fsmd.pdf -- Readings: [1] Pong P. Chu, FPGA Prototyping by VHDL Examples, Wiley, 2008. (Chapters 4,5,6) [2] Samary Baranov, Algorithmic State Machines and Finite State Machines |
|
|
Lecture 5: VHDL Simulation.
Testbenches -- Aldec Active-HDL Simulator and Testbenches: lec05_aldec_simulator.pdf -- More on Testbenches: lec05_testbenches.pdf -- More on FSMs: lec05_more_on_FSMs.pdf -- Example #10: Testbench for fourbit adder circuit -- See above lec05 notes for description -- Example #11: Testbench for fourbit counter -- Example #12: Testbench for edge detection circuit -- Example #13: Testbench for linear feedback shift registers (LFSRs: slides1, slides2) -- Example #14: Testbench for first-input first output (FIFO) buffer -- Example #15: Testbench for UART -- Example #16: Example 1 on Packages (bit8_adder) -- Example #17: Example 2 on Packages (simple ALU) -- Example #18: BCD to Excess-3 converter -- See section 3 of lec05_more_on_FSMs.pdf for description -- Example #19: Bit difference calculator -- See section 4 of lec05_more_on_FSMs.pdf for description -- Readings: [1] Pong P. Chu, FPGA Prototyping by VHDL Examples, Wiley, 2008. (Chapters 7...13) |
fourbit_adder_testbench_vhdl.zip
fourbit_counter_testbench_vhdl.zip edge_detection_testbench_vhdl.zip lfsr_testbench_vhdl.zip fifo_testbench_vhdl.zip uart_testbench_vhdl.zip packages_example1.zip packages_example2.zip bcd_to_excess3_converter_vhdl.zip bit_difference_calculator_vhdl.zip |
|
Lecture 6: Additional examples -- Example #20: Using UART on DE2-115 FPGA board -- Example #21: Digital clock on DE1-SoC FPGA board -- Example #22: Mano's single-cycle computer (SCC); see also D2L for more details -- Example #23: Simple digital camera on DE2-115 FPGA board -- Example #24: "Pong" Game from Ch. 12 & 13 of Pong P. Chu book |
uart_test_impl1_de2115.zip
uart_test_impl1_de1soc.zip cool_digital_clock_impl1.zip (DE2-115 board) digital_clock_de1soc.zip (DE1-SoC board) single_cycle_computer_SCC.zip digital_camera_impl1.zip (DE2-115 board) pong_top.zip (DE1-SoC board) |
Digital Clock (video 4) Fibonacci Number Gen. (video 5) UART (video 6) Pong game (video 7) |
Lecture 7: HPS+FPGA Systems on
DE1-SoC Board -- Basics of working with HPS+FPGA projects: lec07_HPS_FPGA.pdf -- HPS+FPGA projects tutorial - Part1 -- HPS+FPGA projects tutorial - Part2 -- HPS+FPGA projects tutorial - Part3 |
HPS_FPGA_EXAMPLES_PART1.zip
HPS_FPGA_EXAMPLES_PART2.zip HPS_FPGA_EXAMPLES_PART3.zip |
|
Lecture 8: Selected Topics -- Timing analysis -- Instantiation, VHDL vs. Verilog -- OpenCL |
lecture9_timing_analysis.zip |